1. Field of the Invention
The present invention relates to a semiconductor IC unit, more particularly to a semiconductor IC unit provided with both fast operation and low power consumption properties.
The present application follows part of the U.S. patent application No. PCT/JP97/04253 filed on Nov. 21, 1997. The contents of the preceding US patent application are cited and combined with the present application.
2. Description of the Related Art
At present, CMOS integrated circuits (IC) are used widely to form a semiconductor IC unit such as a microprocessor, etc. A CMOS IC consumes an electric power in two ways; dynamic power consumption and static power consumption. The dynamic power consumption is caused by charging and discharging at a switching time and the static power consumption is caused by a subthreshold leakage current. The dynamic power consumption consumes a large current in proportion to the square of a supply voltage VDD, so the supply voltage should be lowered to save the power consumption of the object CMOS IC effectively. In recent years, the supply voltage is thus getting lower and lower to cope with such an object.
On the other hand, some of the power-saving microprocessors available at present are provided with a power management feature and its processor is provided with a plurality of operation modes, so that supply of the clock to an active unit is stopped at its standby time according to the set operation mode.
Since the supply of the clock is stopped such way, it is possible to reduce unnecessary dynamic power consumption in such an active unit as much as possible. However, the static power consumption caused by a subthreshold leakage current cannot be reduced and still remains on the same level at this time.
The operation speed of a CMOS circuit drops at a low supply voltage. In order to prevent such a speed reduction of a CMOS circuit, therefore, the threshold voltage of the MOS transistor must be lowered in conjunction with the drop of the supply voltage. If a threshold voltage is lowered, however, the subthreshold leakage current increases extremely. And, as the supply voltage is getting lower, the static power consumption increases more remarkably due to the subthreshold leakage current, which has not been so much conventionally. This is why it is now urgently required to realize a semiconductor IC unit such as a microprocessor, which can satisfy both fast operation and low power consumption properties.
In order to solve the above problem, for example, the official gazette of Unexamined Published Japanese Patent Application No. Hei-6-53496 has proposed a method for controlling a threshold voltage of MOS transistors by setting a variable substrate bias.
The substrate bias is set to the power source potential for PMOS (P-channel MOS transistors) and the ground potential for NMOS (N-channel MOS transistors) in the active state when the object CMOS circuit is required for a fast operation. On the other hand, in the standby state in which the CMOS is not required for any fast operation, the substrate bias is set to a potential higher than the supply voltage for PMOS and lower than the supply voltage for NMOS (hereafter, this operation will often be referred to as xe2x80x9capplying a bias voltage to a substratexe2x80x9d).
With such a setting of a substrate bias voltage in the standby state, it becomes possible to raise the threshold level of the MOS transistors composing the object CMOS circuit, thereby reducing the static power consumption caused by a subthreshold leakage current.
In order to materialize a semiconductor IC unit such as a microprocessor, etc., which can satisfy both fast operation and lower power consumption properties, the substrate bias must be controlled as described above for each CMOS circuit so that the threshold voltage of the MOS transistors is lowered when the semiconductor IC unit is active and raised when the semiconductor IC unit stands by, thereby reducing the subthreshold leakage current.
As a result of examination, however, the present inventor has found that the following problems still remain unsolved when in controlling the substrate bias in an actual semiconductor IC unit.
(1) A substrate bias controlling circuit must be tested easily as ever.
(2) A CMOS circuit must be prevented from malfunction by controlling the substrate bias.
(3) An increase of a circuit area must be minimized by controlling the substrate bias.
(4) A semiconductor IC unit must be prevented from malfunction when the substrate bias is switched over.
In order to solve the above problems, the present invention has proposed the following means mainly.
To make it easier to test the substrate bias controlling circuit, the output of the negative voltage generating circuit is connected to a pad. In other words, the negative voltage generating circuit must be checked for if a preset voltage level is reached as its output signal. For this check, the negative voltage generating circuit should be provided with a terminal from which the signal is output as it is.
In order to lower the substrate impedance, a plurality of substrate MOS transistors are provided in the main circuit used for controlling the substrate bias. The substrate driving MOS transistors are used to drive the substrate bias when the semiconductor IC unit is active. This is because the impedance must be lowered to fix the substrate potential and suppress the variance of the transistor threshold level when the IC circuit is active, thereby enabling the respective circuits in the main circuit to operate.
The driving power of the semiconductor IC unit increases in the active state more than in the standby state. Preferably, the driving power should thus be 5 times. Ideally, it should be 10 times that in the standby state.
Usually, each circuit becomes unstable when the substrate bias is switched over. In order to prevent this, the gate control signal used for controlling the gate voltage of a substrate driving MOS transistor is wired so that the control signal, after being connected to the substrate driving MOS transistor, is returned to the substrate bias controlling circuit and the potential of the returned signal is used by the substrate bias controlling circuit to detect that the main circuit substrate bias is stabilized.
The semiconductor IC unit is provided with a power-on resetting circuit. The power-on resetting circuit detects that the main circuit is powered. The semiconductor IC unit is kept in the active state so that each substrate driving MOS transistor drives the substrate bias shallowly for a fixed time after the main circuit is powered.
While the semiconductor IC unit is shifted from the standby state to the active state, the substrate bias controlling circuit controls the output impedance of the gate control signal so as to become larger than the impedance to be set after the semiconductor IC unit enters the active state completely.
The semiconductor IC unit is also provided with a negative voltage generating circuit. The substrate bias controlling circuit controls the output impedance of the negative voltage generating circuit in the standby state so as to be smaller than the output impedance in the active state.
The main circuit comprises a plurality of cells. Those cells compose a power-supply net, which is powered by the first metal levels. Another power-supply net is formed with the second wiring layers, which are orthogonal to the first metal levels. And, a switch cell is disposed at each intersection point of the power-supply nets formed with the first and second wiring layers. The power-supply nets of the first and second wiring layers are connected to each other in the switch cells. A substrate driving MOS transistor described above is disposed in each of those switch cells.
The substrate bias supply line of a MOS transistor composing one of the above cells is formed with the first metal levels, which are in parallel to the power-supply net formed with the first metal levels, as well as by the second wiring layers in parallel to the power-supply net formed with the second wiring layers. In the same way as those power-supply nets, the substrate bias supply line formed with the first metal levels is connected to the substrate bias supply line formed with the second wiring layers in each of the switch cells, thereby the gate control signal for controlling the gate voltage of each substrate drive MOS transistor is supplied by the second wiring layers above the switch cell, in parallel to the power-supply net formed by the second wiring layers. The gate control signal is then connected to the gate terminal of the substrate drive MOS transistor in a switch cell described above.
More concretely, the semiconductor IC unit of the present invention comprises a main circuit composed of at least one transistor; a substrate bias controlling circuit used for controlling a voltage to be applied to each transistor substrate; and a standby controlling circuit used for switching between at least two states; active and standby. In the active state, the substrate bias controlling circuit is controlled to increase the subthreshold leakage current flowing in the main circuit. In the standby state, the bias controlling circuit is controlled to decrease the subthreshold leakage current. The semiconductor IC circuit is also provided with a negative voltage generating circuit, which is incorporated in the substrate bias controlling circuit, as well as a terminal for outputting a negative voltage generated from the negative voltage generating circuit to external.
At this time, the semiconductor IC unit is provided with a semiconductor chip having output pads, and a package incorporating the semiconductor chip in itself and having external pins, wherein one of the output pads is used as a terminal, which is not connected to any external pin.
In another embodiment, the semiconductor IC unit is provided with a main circuit composed of at least one MOS transistor, a substrate bias controlling circuit used for controlling a voltage applied to the substrate of the MOS transistor, a standby controlling circuit used for switching the semiconductor IC unit between at least two states of active and standby. The active state allows much subthreshold leakage current to flow in the main circuit and the standby state allows less subthreshold leakage current to flow in the main circuit. The semiconductor IC unit thus controls the substrate bias shallowly in the active state and deeply in the standby state, so that the power for driving the substrate bias shallowly in the active state becomes 10 times or over larger than the power for driving the substrate bias deeply in the standby state.
When the substrate bias is controlled deeply, it should preferably be avoided to operate the main circuit composed of transistors whose substrate is applied a bias voltage respectively. When a bias voltage is applied to the substrate of a transistor, the substrate impedance is high. If a MOS transistor is activated, therefore, the substrate potential is easily changed. Consequently, the MOS transistor will probably malfunction in such a case.
In this embodiment, at least two MOS transistors are used for driving the substrate bias shallowly in the active state. Those MOS transistors are disposed at a distance of 20 xcexcm or over from each other. The gate potential of each of the substrate driving MOS transistors is controlled by the substrate bias controlling circuit.
The gate control signal used for controlling the gate voltage of the substrate driving MOS transistors is returned to the substrate bias controlling circuit after it is connected to the gate of each of the substrate driving MOS transistors. After this, according to the potential of the returned signal, the substrate bias controlling circuit can detect that the substrate bias applied to the main circuit is stabilized.
Preferably, the threshold voltage of the substrate driving MOS transistors should be set larger than the threshold level of the MOS transistors composing the main circuit. If the semiconductor IC unit is provided with an I/O circuit used for interfacing with external, at least one of the MOS transistors composing the I/O circuit should preferably be coated with an oxidization film thicker than the oxidization film of the MOS transistors composing the main circuit. Such way, the withstand voltage should preferably be set high at portions to which a high voltage is applied.
The semiconductor IC unit is further provided with a power-on resetting circuit used for detecting that the main circuit is powered. The active state is kept for a fixed time after the main circuit is powered. In the active state, each substrate MOS transistor drives the substrate bias shallowly.
In another embodiment of the present invention, the semiconductor IC unit is provided with two supply voltages; the first (VDDQ) and the second (VDD). The first supply voltage has its absolute value larger than that of the second supply voltage, which is 2V or under. The second supply voltage (VDD) is supplied to the main circuit (LOG) and the first supply voltage (VDDQ) is supplied to both substrate bias controlling circuit (VBC) and standby controlling circuit (VBCC) . The first supply voltage is applied earlier than the second supply voltage. The substrate bias controlling circuit controls so as to keep the main circuit in the active state for a fixed time after the substrate bias controlling circuit is applied the second supply voltage.
Furthermore, if the output impedance of the gate control signal of the substrate driving MOS transistors in a process in which the state is shifted from standby to active is set higher than that after the state is already set in the active state, it becomes possible to adjust the speed for shifting the state from standby to active so as to suppress the inrush current low in the shifting process.
Furthermore, if the output impedance of the gate control signal of the substrate driving MOS transistors in a process in which the state is shifted from standby to active is set higher than that after the state is already set in the active state, it becomes possible to adjust the speed for shifting the state from standby to active so as to suppress the inrush current low in the shifting process. It also becomes possible to detect by the returned signal that the main circuit is already set in the active state.
It is also possible to set the amplitude of the gate control signal larger than the gate breakdown voltage of the substrate driving transistors.
Furthermore, the semiconductor IC unit is provided with a negative voltage generating circuit, so that the substrate bias controlling circuit can control the output impedance of the negative voltage generating circuit in the standby state lower than that in the active state.
Another embodiment of the present invention is a semiconductor IC unit, wherein the negative voltage generating circuit is provided with the first and second charging pump circuits, so that the substrate bias controlling circuit uses the first charging pump circuit in the standby state and the second charging pump circuit in the active state thereby to generate a negative voltage respectively. In addition, the pumping capacitor of the first charging pump is set smaller than that of the second charging pump circuit.
The semiconductor IC unit may also be composed so that the negative voltage generating circuit can generate the third supply voltage in addition to the first and second supply voltages so that the first supply voltage is larger than the second supply voltage, which is 2V or under, and the main circuit is supplied the second supply voltage while the substrate bias controlling circuit and the standby controlling circuit are supplied at least the first supply voltage and the substrate bias controlling circuit controls the substrate bias of PMOS transistors so as to be adjusted to the second supply voltage potential in the standby state and the substrate bias of NMOS transistors so as to be adjusted to the third supply voltage potential thereby to satisfy (the third supply voltage)=(the first supply voltage)xe2x88x92(the second supply voltage).
Furthermore, the negative voltage generating circuit is provided with at least a charging pump circuit, a comparator, the first reference voltage circuit used for generating a potential of a half of the second supply voltage one, and the second reference voltage circuit used for generating an intermediate potential between the first and third supply voltages. The comparator compares the voltage output from the first reference voltage circuit with the voltage output from the second reference voltage generating circuit thereby controlling at least one of the charging pumps to stabilize the third supply voltage.
The first and second reference voltage generating circuits are composed respectively of a serial circuit in which same type conductor MOS transistors are connected serially. In each of the conductor MOS transistors, the substrate terminal is connected to the source terminal and the gate terminal is connected to the drain terminal. Each of the first and second reference voltage generating circuits can be selected so as to operate a plurality of MOS transistors in a saturation area. It may also be composed so as to have Schmitt characteristics.
The main circuit is composed of a plurality of cells. A power-supply net for those cells is powered by the first metal levels. Another power-supply net is formed with the second wiring layer above those first metal levels so as to be orthogonal to those first metal levels. And, a switch cell is disposed at each intersection point of the power-supply nets formed with the first and second wiring layers, so that both power-supply nets formed with the first and second wiring layers are connected to each other in such the switch cells. In addition, a substrate driving MOS transistor is disposed in each of those switch cells.
A switch cell may also be composed so as to dispose a decoupling capacitor between a power source and a ground.
In addition, above the power-supply net formed with the second wiring layers is disposed a power-supply net formed with the fourth wiring layers, which are in parallel to the power-supply net formed with the second wiring layers. The power-supply nets formed with the second and fourth wiring layers may be connected to each other outside those switch cells.
There is another power-supply net formed with the fifth wiring layers. The power-supply net is connected to the power-supply net formed with the fourth wiring layers in switch cells. A power source mesh formed with the power-supply nets of the fourth and fifth wiring layers may be rougher than the power source mesh formed with the power-supply nets formed with the first and second wiring layers. And, the fourth and fifth wiring layers may be thicker than any of the first and second wiring layers.
The substrate bias supply lines of the MOS transistors composing cells respectively may be formed with the first metal levels in parallel to the power-supply net formed with the first metal levels, as well as in parallel to the power-supply net formed with the second wiring layers. Just like the power-supply nets described above, the substrate bias supply lines formed with the first metal levels may be connected to the substrate bias supply lines formed with the second wiring layers in switch cells.
The gate control signal used for controlling the gate voltage of each of the substrate driving MOS transistors may be supplied by the second wiring layers formed above switch cells, which are disposed in parallel to the power-supply net formed with the second wiring layers and connected to the gate terminal of each of the substrate driving MOS transistors in a switch cell.
The substrate bias supply lines wired by the second wiring layers above the switch cells and the gate control may be disposed between the power-supply nets wired by the second wiring layers above switch cells.
The semiconductor IC unit of the present invention is also provided with a data path circuit. The data flowing direction of the data path circuit may be in parallel to the power-supply net wired by the first metal levels used for a plurality of cells.
The substrate bias can be set so as to raise the threshold level of at least one MOS transistor when the semiconductor IC unit of the present invention is selected.
In another embodiment of the present invention, in a charging pump circuit composed of the first and second pumping capacitors, the first and second (two) P-channel transistors, the first and second (two) N-channel transistors, and an oscillating circuit, the first pumping capacitor, the first P-channel transistor, and the first N-channel transistor are used for pumping the electric charge of the first pumping capacitor when the output of the oscillating circuit is xe2x80x98Hxe2x80x99 and the second pumping capacitor, the second P-channel transistor, and the second N-channel transistor are used for pumping the electric charge of the second pumping capacitor when the output of the oscillating circuit is xe2x80x98Lxe2x80x99.
In further another embodiment of the present invention, the semiconductor IC unit is provided with a main circuit (LOG) including transistors composed on a semiconductor substrate respectively and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to each substrate. The main circuit is provided with switch transistors (MN1 and MP1) used for controlling a voltage to be applied to each substrate and receives control signals output from the substrate bias controlling circuit through the gate of each of the switch transistors. The control signals may be composed so as to be returned to the substrate bias controlling circuit.
Each switch transistor is disposed in a rectangular switch cell and each of other transistors is disposed in a rectangular standard cell. A switch cell and a standard cell should preferably be disposed side by side in terms of the layout.
The power sources (VSS and VDD) used for driving the transistors (MN2 and MP2) in the main circuit, as well as the power sources (vbp and vbn) of the substrate bias supplied from the substrate bias controlling circuit should preferably be wired so as to cross both switch cells and standard cells vertically in the direction those cells are disposed.
The threshold level of the switch transistors should preferably be larger than that of other transistors in terms of the transistor resistance.
The switch transistors (MN1 and MP1) should preferably be inserted between the driving power sources (VSS and VDD) for the transistors in the main circuit and the power sources (vbp and vbn) of the substrate bias supplied from the substrate bias controlling circuit in terms of the layout.
The source or drain of each transistor can be connected to the driving power sources (VSS and VDD) and the transistor substrate potential can be connected to the substrate bias power sources (vbp and vbn).
The substrate bias controlling circuit can detect that control signals (vbp and vbn), after they are output, have been returned via the main circuit as control signals (vbpr and vbnr), then have reached a predetermined voltage.
Then, the substrate bias controlling circuit can generate a detection signal (vbbenbr), thereby stabilizing the operation of the main circuit.